`include "cpu_def.vh"

module branch_judge(
  input                   valid,
  input [`NR_BR_OP - 1:0] br_op,
  input [           31:0] rf_rdata_0,
  input [           31:0] rf_rdata_1,

  output br_taken
);

  wire ne  = |(rf_rdata_0 ^ rf_rdata_1);
  wire eq  = ~ne;
  wire eqz = ~(|rf_rdata_0);
  wire gez = ~rf_rdata_0[31];
  wire ltz = rf_rdata_0[31];
  wire gtz = gez && !eqz;
  wire lez = ltz || eqz;

  assign br_taken = (
    br_op[`OP_BEQ   ] &&  eq ||
    br_op[`OP_BNE   ] &&  ne ||
    br_op[`OP_BLTZ  ] && ltz ||
    br_op[`OP_BGEZ  ] && gez ||
    br_op[`OP_BLEZ  ] && lez ||
    br_op[`OP_BGTZ  ] && gtz ||
    br_op[`OP_BLTZAL] && ltz ||
    br_op[`OP_BGEZAL] && gez ||
    br_op[`OP_J     ]        ||
    br_op[`OP_JAL   ]        ||
    br_op[`OP_JR    ]        ||
    br_op[`OP_JALR  ]
  ) && valid;

endmodule
